In such a board, the multi-layer structure is ordinarily supported by a substrate made of an insulating slab that incorporates the distribution planes of the supply voltages of the integrated circuit or circuits. The substrate may be a slab of co-fired ceramic, or a slab made of some organic material, such as plastic. However, the board may be simply formed of the multi-layer structure, taking the form of a flexible board.
Alternatively, the board may be a slab of semiconductor material incorporating integrated circuits and covered with a multi-layer structure for interconnection of these integrated circuits by the WSI (wafer scale integration) technique. In all these boards, the multi-layer structure comprises a stack of alternating conductive and insulating layers. In this stack, an insulating layer is pierced with via-holes for electrical connection of the adjacent conductive layers. The conductive layer is ordinarily made of aluminum or copper, and at present, the insulating layer is preferably made of a polymerized material such as polyimide.
One problem in the manufacture of the multi-layer structure is in obtaining relatively planar layers. One conventional manufacturing method comprises forming the conductors of a conductive layer and covering the conductive layer with an insulating layer of polymerizable material in the form of viscous liquid, known in this field as paste. This paste has the advantage of having a surface area with steps or lower levels that are not as high as the corresponding edges of the conductors underneath. This method may comprise spreading a drop of polymerizable material by centrifugal force, or spray application of the paste, or making a coating of the paste, for example by serigraphy. The paste is then polymerized. Naturally this method is used under conditions that lend the polymerized layer the great thickness required to assure the desired insulating between two conductive layers one on top of the other. The insulating layer is covered with a mask that defines the location of the via-holes to be formed. In a conventional embodiment, the via-holes are flared, and the conductors of the upper conductive layer extend on the insulating layer and on the walls of the via-holes that have just been formed, as well as over the regions of the conductors making up the bottom of the via-holes. The result is an upper conductive layer provided with numerous depressions at the level of the via-holes. Understandably, stacking numerous layers accentuates the depth of the depressions and consequently entails the risk of creating discontinuities in the conductive layers deposited. Moreover, the formation and flaring of the via-holes are delicate steps in the method.
One improvement to this method comprises avoiding the superposition of via-holes by offsetting them in a spiral about a vertical line. A first disadvantage of this is that it reduces the density of the via-holes in the same insulating layer and consequently reduces the overall density of conductors in the multi-layer structure. A second advantage is that although the staggered disposition of the via-holes is quite fast, it limits the number of reliable layers in the structure. For example, disposing them in a spiral 90.degree. from one another means that a via-hole in the fifth layer is superimposed on a via-hole of the first layer and undergoes the deformations occasioned by the four via-holes in between. In practice, this method is ordinarily limited to the deposition of on the order of five superimposed conductive layers.
A more recent solution to the problem has been to form vias on the conductors of a conductive layer and to cover all of this with a paste that is polymerized to obtain the insulating layer. The insulating layer has the great thickness required to assure the desired insulation between two superimposed conductive layers and covers the vias with a lesser thickness of insulating material. The insulating layer is covered with a mask that has the configuration of the via-holes. Next, a selective attack of the insulating layer is performed to uncover the upper surfaces of the vias and to flare the via-holes. Because of the vias, these via-holes are markedly less deep than those obtained by the method described in the previous paragraph. The upper conductive layer is accordingly relatively more flattened or planarized.
The problem that this solution presents will become quite clear from the following example of a conventional method of forming a polymerized insulating layer on a conductive layer provided with vias. It is assumed that the conductive layer is formed on a plane reference surface composed of conductors having a height provided with vias of height hH with respect to the reference surface. A drop of a viscous polyamic acid paste is deposited on this conductive layer. By rotation, the drop spreads over the entire conductive layer along a thickness T0 which is a function of the viscosity of the paste, the speed of rotation, and the relief of the conductive layer. In an oven, prefiring of the paste is performed. The temperature of the prefiring must be less than the temperature of imidization (on the order of 220.degree. C.) at which the polymerization of the paste begins. The prefiring solidifies the polyamic acid and eliminates some of the solvent incorporated in the paste. The amount of solvent eliminated depends on the prefiring temperature, which in practice is between 130 and 200.degree. C. The thickness T1 of the prefired layer depends on the quantity of solvents remaining in the layer and consequently on the pre firing temperature and on the nature of the paste. The thickness T1 of a standard prefired face in the vicinity of the imidization temperature may be reduced to approximately 40% of the thickness T0 of the paste. The prefired layer is then polymerized, at a temperature ordinarily on the order of 400.degree. C. The resulting polyimide layer has a thickness T2 that is less than the thickness T1 by a magnitude depending on the nature of the paste and on the prefiring temperature. In total, for an ordinary paste, the thickness T2 is on the order of 50% of the thickness T0 of the initial paste layer. The polyimide surface is entirely planar and has steps at the level of the edges of the conductors and of the vias.
Let s be the height of the step relative to the h of a conductor, and let S be the height of a step relative to the height H of a via with respect to the surface of the insulating layer underneath it. The planarization factor of the insulating layer is defined by a number currently known as the DOP factor (degree of planarization)=1-s/h. This formula is valuable regardless of the value h and as long as the height of the paste initially spread over the conductive layer is substantially equal to or greater than the value h. Consequently, under the same conditions, the DOP factor=1-S/H. The DOP factor of a current standard layer is on the order of 0.4. This means that if h=5 micrometers, s=3 micrometers, and if H=20 micrometers, S=12 micrometers.
The size of the step S due to the vias currently makes it necessary to reduce the height H of the vias. However, the insulating layer must have a relatively high minimum thickness to assure good electrical insulation between the superimposed conductive layers. Hence if the height of the vias is not great, it is necessary to make relatively deep via-holes in the insulating layer. With the current standard products, the practice of introducing vias into the conductive layer makes a relatively slight improvement, for improving the planarity of an insulating layer, compared with the conventional method described above. To reduce the height of the steps, manufacturers are currently studying products having a higher DOP factor. However, in conventional technology the steps remain and must be opened, uncovering the upper faces of the vias, in order to form via-holes. Forming the via-holes is a delicate operation. It in fact requires the deposition of a mask and the very precise position of openings defining the locations of the via-holes above the vias. Furthermore, the duration of etching is conventionally determined by optical means, which detect the appearance of the metal of the vias. In the present case, these optical means must act inside the via-holes, which makes the detection of the metal difficult. If the detection is done prematurely, then the presence of a remaining film of polyimide will affect the electrical quality of the contact of the via with the upper conductive layer.
Hence the current problem is of using ordinary pastes which are less expensive and are reliable, to obtain a substantially planar surface regardless of the height of the vias of the conductive layer below it, and of no longer making via-holes in the substantially planar insulating layer. Hence this method would have the advantage of stacking a large number of reliable conductive layers, which are insulated correctly and reliably by substantially planar insulating layers. Such a method is the subject of the invention.